Model Me, Model World
Blayground
RISC-V I Tool sets
Much of the RISC-V resource was publicized on GitHub. But as git-submodule is used, it’s possible that if a small tool module is updated but a larger project which adopts this module will not update this module until some contributor manually update the .gitmodules file. Before that, one has to check if the newer version of the sub-module is compatible with current project. It is at our own risk to update a sub-module without testing out its compatibility.
In an essence of saving time, the following table was intended to figure out the dependencies between this bunch of codes.
| Repo | Submodule | Description |
|---|---|---|
| rocket-chip | v | Rocket Chip Generator |
| rocket | Rocket Microarchitectural Implementation of RISC-V ISA | |
| chisel | ||
| uncore | ||
| hardfloat | @berkeley-hardfloat | |
| dramsim2 | @DRAMSim2 | |
| riscv-tools | see below | |
| fpga-zynq | see below | |
| riscv-tools | v | RISC-V Tools (GNU Toolchain, ISA Simulator, Tests) |
| riscv-gcc | gcc+newlib and gcc+glibc toolchains | |
| riscv-llvm | clang compiler* | |
| riscv-fesvr | RISC-V Frontend Server | |
| riscv-pk | RISC-V Proxy Kernel | |
| riscv-isa-sim | RISC-V Functional ISA Simulator spike | |
| riscv-qemu | QEMU with RISC-V Emulation Support | |
| riscv-opcodes | RISC-V Opcodes | |
| riscv-tests | submodule env @riscv-test-env | |
| fpga-zynq+ | v | Ready to use prebuild binaries, reference linked to amazon servers.+ fpga-images-zedboard, fpga-images-zybo, fpga-images-zc706. |
| Linux-Digilent-Dev | Fork of linux for the Zybo. For use in the Zybo RISC-V Rocket tutorial. | |
| u-boot-Digilent-Dev | Fork of u-boot for the Zybo. For use in the Zybo RISC-V Rocket tutorial. | |
| riscv-linux | ||
| riscv-gnu-toolchain | GNU toolchain for RISC-V, including GCC 4.9.2. Maybe a newer version of riscv-gcc+ | |
| riscv-sodor | educational microarchitectures for risc-v isa | |
| chisel | ||
| chisel-tutorial | chisel tutorial exercises and answers | |
| chisel-sift | SIFT processing pipeline in Chisel(under development)* | |
| riscv-angel | JavaScript RISC-V ISA Simulator. Boots linux in a web-browser. | |
| misc | ||
| homebrew-riscv | ||
| riscv-clang | ||
| ccbench | Memory System Microbenchmarks | |
| bits | Firebox Benchmarks |
The above table tried to explain these bunch of repositories and their functionalities as well as their dependencies.
In consistent with the hierarchy of the above table suggests, three comprehensive tutorials are present in rocket-chip, riscv-tools and fpga-zynq repositories covering about hardware description, simulation & build toolchain and FPGA verification respectively. One who is interested in this topic is recommended to read these documents thoroughly.